Mainstream processor chips, both in high performance and low power segments, are increasingly integrating additional functionality such as graphics, display engines, security engines, PCIe™ ports (i.e., ports in accordance with the Peripheral Component Interconnect Express (PCI Express™ (PCIe™)) Specification Base Specification version 2.0 (published 2007) (hereafter the PCIe™ specification) and other PCIe™ based peripheral devices, while maintaining legacy support for devices compliant with a PCI specification such as the Peripheral Component Interconnect (PCI) Local Bus Specification, version 3.0 (published 2002) (hereafter the PCI specification).
Such designs are highly segmented due to varying requirements from the server, desktop, mobile, embedded, ultra-mobile and mobile Internet device segments. Different markets seek to use single chip system-on-chip (SoC) solutions that combine at least some of processor cores, memory controllers, input/output controllers and other segment specific acceleration elements onto a single chip. However, designs that accumulate these features are slow to emerge due to the difficulty of integrating different intellectual property (IP) blocks on a single die. This is especially so, as IP blocks can have various requirements and design uniqueness, and can require many specialized wires, communication protocols and so forth to enable their incorporation into an SoC. As a result, each SoC or other advanced semiconductor device that is developed requires a great amount of design complexity and customization to incorporate different IP blocks into a single device. This is so, as a given IP block typically needs to be re-designed to accommodate interface and signaling requirements of a given SoC.
Thus a system can include a mix of PCI and PCIe™ devices. At the time of its creation, the original PCI specification did not contain concepts and semantics that were later introduced in the PCIe™ specification. One of these semantics introduced by the PCIe™ specification is an Unsupported Request (UR) completion response. This response provides an indication from a PCIe™ device to an upstream component that it cannot handle a particular request and thus it responds with the UR completion response. In contrast, the PCI specification did not provide such a response. Instead, according to the PCI specification, when a device is unable to handle a request, it de-asserts a device select signal (DEVSEL#) to indicate to the upstream device that it cannot handle the request. As a result, the transaction master aborts and the PCI device is not involved in logging and reporting of Unsupported Requests.